Logic Synthesis of Reversible Wave Cascades

A circuit is reversible if it maps each input vector into a unique output vector, and vice versa. Reversible circuits lead to power-efficient CMOS implementations. Reversible logic synthesis may be applicable to optical and quantum computing. Minimizing garbage bits is the main challenge in reversible logic synthesis. This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms (called here reversible wave cascade) implementing incompletely specified Boolean functions. The remarkable property of the presented method compared to other reversible synthesis methods is that it creates at most one constant input and no additional garbage outputs. Preliminary estimation suggests that the method may be applicable to small and medium-sized benchmarks.